This relates to semiconductor devices such as finFETs (Fin Field Effect Transistors). FinFETs are also referred to sometimes as multiple-gate, double-gate or tri-gate transistors.
FinFETs have been developed to obtain larger gate widths A fin is a thin segment of semiconductor material standing on edge, thereby making available multiple surfaces for the formation of gate structures. The fins have first and second major surfaces that are opposite one another and usually are symmetric about a center plane that bisects the fin lengthwise. The major surfaces are often illustrated as being parallel as in U.S. Pat. No. 7,612,405 B2 or Pub. No. US2008/0128797 A1, which are incorporated herein by reference; but process limitations usually result in surfaces that slope outwardly from top to bottom of the fin with the result that the cross-section of the fin is trapezoidal in shape. In some cases, the two major surfaces meet at the top. In some embodiments, a separate gate structure may be located on each surface of each fin. In other embodiments, there is a common gate structure for all surfaces.
Doped source and drain regions are located on opposite sides of the gates. As in a planar FET, a voltage applied to the gate controls current flow in a channel that extends between the doped source and drain regions in the semiconductor beneath the gate.
Further details on finFETs may be found at pages 137-138 of N. H. E. Weste and D. Harris, CMOS VLSI Design (Pearson, 3rd ed., 2005) which are incorporated herein by reference.
One application of finFETs is in the memory cells of a static random access memory (SRAM). The basic structure of a SRAM memory cell is a latch having a first pair of series-connected PMOS and NMOS transistors cross-coupled with a second pair of series-connected PMOS and NMOS transistors and two NMOS pass transistors for connecting the latch to two bit lines. It is highly desirable to use finFETs to implement the PMOS and NMOS transistors in such cells to take advantage of the small size and high switching speeds of the finFETs. However, when conventional SRAM finFETs are implemented in silicon germanium, the PMOS finFETs are observed to have high DC leakage. High leakage currents not only degrade the operation of the finFET but also produce excessive heating of the semiconductor chip in which the PMOS transistors are formed. This is especially troublesome in circuits where large numbers of PMOS transistors are used such as the configuration random access memory (CRAM) circuits of field programmable gate arrays (FPGAs) that may include millions of memory cells.